The advent of integrated circuits has clearly demonstrated the benefits which can be achieved by making electrical devices smaller and smaller. In a similar way, structures like weak-link devices which include microbridges and Josephson tunnelling devices also benefit from being made smaller and smaller. On a less exotic level, to the extent that metal lines having submicron dimensions are now being made, interconnections between levels of such metal layers must also be of a size which are compatible with the line dimensions. Presently used approaches are sometimes less than satisfactory in that the implementation of the resulting structures requires a good deal of chip area and may require several photolithographic masking and etching steps. As will be seen from a consideration of the prior art discussed hereinbelow, a number of different approaches have been used which incorporate electron beam or other type resists. In another approach, holes are simply formed in insulation layers and conductive material deposited therein to form a conductive interconnection.
U.S. Pat. No. 4,197,332 filed Feb. 12, 1979 shows the fabrication of contamination resist cones. The technique of this patent in the formation of contamination resist cones is utilized in the present application and is herewith incorporated by reference.
U.S. Pat. No. 4,224,630 filed Aug. 25, 1978 shows a SQUID comprised of two superposed superconductive layers with an insulating layer therebetween. A plurality of holes through the insulating layer filled with superconductive material form weak links between the layers. The structure is formed using standard photoresist procedures to pattern the holes in the insulation layer. Thereafter, superconducting material is formed over the insulator and in the holes.
U.S. Pat. No. 4,430,790 filed July 21, 1982 shows a triple layer superconducting device which comprises a superconductor-insulator-superconductor laminar arrangement on a substrate. A weak-link extends from one of the superconductor layers to the other across the thickness of the intervening separator. The resulting structures are characterized as "quasi-planar" devices as opposed to the structures of the present invention which are totally planar.
U.S. Pat. No. 3,689,780 filed Aug. 14, 1969 shows a number of weak-link structures which are formed between layers of superconducting materials. FIG. 8 of this reference shows a conical superconductor over which a weak-link material is formed. A pair of superconductive elements then contact the weak-link material on opposite sides thereof.
U.S. Pat. No. 3,846,166 filed Sept. 25, 1972 shows a pattern conductive layer over which an insulating layer is formed. The insulating layer is etched forming a truncated cone-like structure. A final layer of conductive material is deposited in the etched holes and over the top of the insulation forming interconnections between two levels of conductive material.
It is, therefore, a principle object of this invention to provide an interconnection device wherein the interconnection means may be an element of normal metal, an element of superconducting metal, an element of low bandgap insulator material, an element of semimetal material or an element of semiconductor material.
Another object is to provide an interconnection structure which is planar and therefore suitable for integrated circuit applications.
Still another object is to provide a fabrication method which utilizes contamination resist cones or portions thereof to provide interconnection structures with nanometer dimensions.
It is yet another object of the present invention to provide a fabrication method wherein the thickness of a conductor sandwiched insulation layer determines the length of the interconnection means.